# IBM Discloses 0.7-Nanometer Transistor Process Using Vertically Stacked Devices

The company describes a three-dimensional nanostack architecture at what it calls 7-angstrom scale, pointing to continued density gains beyond today's leading nodes.

- Published: 2026-06-26T10:45:35.415Z
- Canonical: https://polylog.news/ai/2026-06-26/ibm-discloses-0-7-nanometer-transistor-process-using-vertica
- Publisher: Polylog (AI desk)
- Section: tech
- Sources: [Polylog editors](https://polylog.news)

IBM has presented what it describes as a breakthrough in sub-one-nanometer chip technology, [according to the Russian-language channel AI ML Big Data](https://t.me/ai_machinelearning_big_data/10404). The reported process operates at 0.7 nanometers, or 7 angstroms, and uses a three-dimensional nanostack transistor architecture in which devices are stacked vertically and offset relative to one another.

Two cautions apply. First, process node names have long been marketing labels rather than literal physical dimensions, so 0.7 nanometer describes a generation, not a measured gate length. Second, a research disclosure is years removed from high-volume manufacturing. IBM has historically demonstrated advanced nodes in its research line well ahead of any foundry shipping them, and the path from a demonstrated stack to working wafers is where most such announcements slow down.

What is substantive is the architectural direction. Stacking transistors vertically is the industry's main remaining method for raising density once lateral scaling of fin and gate-all-around devices runs out. If the approach succeeds in production, it extends the trajectory of transistors per unit area that underpins the cost curve of AI accelerators.

For now this is a capability demonstration attributed to a single secondary report, not a product. Its importance comes from its continuity with where leading-edge logic has been moving, not from any near-term effect on chip supply.

## What this means

The economics of training and serving large models track transistor density and cost per operation. Any credible path to denser logic at sub-nanometer scale keeps long-run compute costs falling, which is the assumption built into every multi-year AI infrastructure plan.

## What to watch

- Whether IBM or a foundry partner attaches yield, performance, and timeline figures to the 0.7-nanometer process, which would distinguish a research result from a manufacturable node.
- Adoption of three-dimensional stacked-transistor designs by the major logic foundries, the signal that vertical scaling is becoming the mainstream successor to gate-all-around devices.