# Samsung Plans to More Than Double Output of HBM4 and HBM4E Memory Next Year

The expansion targets Nvidia's next accelerator generation, where memory bandwidth, not logic throughput, is the upper limit on inference performance.

- Published: 2026-09-21T06:21:17.793Z
- Canonical: https://polylog.news/ai/2026-09-21/samsung-plans-to-more-than-double-output-of-hbm4-and-hbm4e-m
- Publisher: Polylog (AI desk)
- Section: markets
- Sources: [Seoul Economic Daily](https://en.sedaily.com/finance/2026/09/20/samsung-to-double-hbm4-output-next-year-sources-say), [TweakTown](https://www.tweaktown.com/news/108260/samsung-accelerates-hbm4e-process-aims-for-3-25tb-sec-bandwidth-ready-for-nvidia-rubin-ai-gpus/index.html)

Samsung Electronics intends to more than double production of high-bandwidth memory (HBM), specifically its HBM4 and HBM4E generations, next year, [the Seoul Economic Daily reported](https://en.sedaily.com/finance/2026/09/20/samsung-to-double-hbm4-output-next-year-sources-say), citing people familiar with the plan. Samsung has not confirmed the figure publicly, and the report should be read as a supply chain signal rather than a company commitment.

The context is that high-bandwidth memory has become the scarce input in accelerator manufacturing. A modern training or inference part is bandwidth-bound long before it is compute-bound, which is why the memory vendors, rather than the logic foundries, now hold the limiting position in the supply chain. Samsung has been pushing its HBM4E process toward higher per-pin speeds, [with reported targets in the range of 3.25 terabytes per second of package bandwidth](https://www.tweaktown.com/news/108260/samsung-accelerates-hbm4e-process-aims-for-3-25tb-sec-bandwidth-ready-for-nvidia-rubin-ai-gpus/index.html) aimed at Nvidia's next generation of parts. Separate reporting describes a custom eight-layer HBM4E variant built to Nvidia's specification.

Samsung's strategic position matters as much as the volume. SK Hynix has held the lead in high-bandwidth memory qualification for several accelerator generations, and Samsung's re-entry at scale changes the bargaining structure on the buyer side. A second qualified supplier at volume converts memory from a single-source dependency into a contestable one, which tends to compress prices and shorten lead times even when the nominal capacity addition is modest.

Treat the doubling figure with appropriate caution. Memory capacity plans are announced on a rolling basis, revised frequently, and depend on yields that are not disclosed. What is verifiable is the direction: all three major suppliers are adding HBM4-class capacity into 2027, and accelerator vendors are specifying bandwidth rather than capacity as the design constraint.

## What this means

If Samsung reaches volume qualification, the direct effect is on the input cost of every accelerator that ships with high-bandwidth memory, which flows through to the cost of serving large-context models. The beneficiaries are accelerator designers with dual-sourced memory, notably Nvidia, and the hyperscalers buying at scale. The party most exposed is SK Hynix, whose pricing power rests on being the preferred qualified supplier. For model builders, cheaper and more plentiful memory capacity specifically eases the constraint that makes large sparse models expensive to serve, since those models need the weights resident even when most experts stay idle.

## What to watch

- Whether Samsung announces formal qualification for Nvidia's next accelerator generation, which converts a production plan into contracted revenue.
- Spot and contract pricing for high-bandwidth memory into 2027, since falling prices would confirm supply is catching demand and rising prices would show the bottleneck persists.
- Whether accelerator vendors respond by raising the memory capacity on mainstream parts, which would make large sparse open-weight models economical to self-host.