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Morning Edition · Tuesday, July 28, 2026Published at 1:47 AM EDT · New York

Nvidia Puts Its Own Vera CPUs Into the Loop for Designing Next-Generation Chips

Early testing shows the 88-core processor running Cadence and Synopsys verification tools about 1.5 times faster than an AMD Epyc baseline, aimed at the 2028 Rosa CPU.

Nvidia Puts Its Own Vera CPUs Into the Loop for Designing Next-Generation Chips

Nvidia said it is deploying its Vera CPU across the electronic design automation (EDA) workflows it uses to develop its next generation of CPUs and GPUs, working with Cadence and Synopsys to optimize their tools for the processor. Vera, lau…

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AI Compresses the Chip Design Loop

Chip vendors increasingly apply their own accelerators and AI agents to EDA and verification, shortening design cycles and pulling engineering compute toward their own silicon.