AI Agents Beat Published Quantum Circuit and Decoder Designs at IBM and Anthropic, and an Open-Weight Chinese Model Did It for $26

Three results in one week, collected by the AI Post channel, show agentic models doing verifiable optimization work on quantum hardware. All three include explicit correctness checks, which separates them from demonstrations.

On October 13 IBM Research described an "agent factory" in which a coordinator agent plans the search and assigns optimization hypotheses to four worker agents. Each worker rewrites the C++ kernel of a decoder, and a verifier checks every candidate for correctness. The target was a decoder for the [[144,12,12]] bivariate bicycle "gross" code running Relay-BP, the algorithm behind IBM's fault-tolerance roadmap. Driven by Claude Opus 5, the system found a design 204 times faster than its starting point for an estimated $299 of inference. With GLM-5.3, an open-weight model from China's Z.ai, it cut estimated latency 52-fold for about $26, which Quantum Computing Report puts at 11.5 times lower inference cost. Both speedups are estimates measured against IBM's own starting design, not against a production decoder.

On October 16 Anthropic published work from its STEM Fellows Program, done with Harvard's Susanne Yelin and Mikhail Lukin. In it, Claude Mythos 5 redesigned eight commonly used quantum circuits from plain-language specifications. The model writes Python programs that generate circuits. An independent evaluator rejects any circuit that fails its task and scores the rest by Toffoli count multiplied by peak qubit count. Claude beat the best published designs on seven of the eight tasks, with gains of up to 39 times on that metric. One 53-hour run produced an elliptic-curve circuit with 17 times fewer gates than the smallest previous design, at a cost of 12% more qubits. The preprint went up on October 15 and has not been peer reviewed.

The same week, Google Quantum AI published a Science paper showing magic state cultivation on its Willow processor. The technique cut errors in the non-Clifford T-states needed for universal computation by about 40 times. Older distillation protocols were projected to consume most of a fault-tolerant machine's physical qubits.

A new arXiv paper applies the same verify-then-reward pattern to classical chip design. Takeshita and colleagues train an LLM with multi-objective RL to generate register-transfer level (RTL) circuits spread along the power, performance and area (PPA) Pareto front instead of collapsing the objectives into one scalar reward. A reward based on each design's hypervolume contribution raised relative hypervolume by 13.3 percentage points over the baseline and by 14.4 points over single-objective training.